Partitioning method and system for 3D IC

ABSTRACT

A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.

FIELD

This disclosure relates generally to semiconductor fabrication, and morespecifically to three dimensional integrated circuits (3D IC).

BACKGROUND

Developments in integrated circuit technology have often focused onimproving the integration density of various electronic components (e.g.transistors, capacitors, diodes, resistors, inductors, or the like) intoa given chip or wafer area. Various improvements have reduced componentsizes, permitting more components to be integrated on the surface of thesemiconductor die. Such two-dimensional (2D) integration densityimprovements are physically limited by device size, the size of the die,and other limitations including the complexity of design.

IC packaging has evolved, such that multiple ICs may be verticallystacked in so-called three-dimensional (“3D”) packages in order to savehorizontal area on a printed circuit board (“PCB”). Some 3D IC packagesinclude the use of through substrate vias (TSV), also referred to asthrough-silicon-vias, in the case of silicon-based dies. The inclusionof TSV increases the complexity of semiconductor fabrication andpackaging. For example, TSV-to-TSV coupling is an additional noisesource for 3D IC packages.

Another form of 3D IC integrates the fabrication process in two or morestacked tiers. Each tier has a semiconductor or dielectric layer and aninterconnect structure. If an upper tier includes active devices, thatupper tier has a thin semiconductor substrate or layer over theinterconnect structure of the adjacent lower tier. An upper tierinterconnect structure connects the devices in the upper tier to oneanother and to external pins. Inter-tier vias (also referred to asinter-level vias, ILV) provide additional connections between lower tierdevices and upper tier devices.

SUMMARY

In some embodiments, a method comprises: receiving a circuit designcomprising networks of first devices fabricated by a first fabricationprocess; selecting second devices to be fabricated by a second process;substituting the second devices for the first devices in the networks ofthe circuit design; sorting the second devices within a selected one ofthe networks by device area from largest device area to smallest devicearea; and assigning each second device in the selected network to befabricated in a respective one of a plurality of tiers of a 3D IC forwhich a total area of second devices previously assigned to that tier issmallest, the second devices being assigned sequentially according tothe sorting.

In some embodiments, a method comprises; receiving a circuit designcomprising networks of first devices fabricated by a first fabricationprocess; identifying a first one of the networks included in the circuitdesign, wherein the first network includes an equal number of p-metaloxide semiconductor field effect transistors (p-MOSFET) devices andn-MOSFET devices; selecting a first subset of a plurality of seconddevices to be fabricated by a second process, the first subset includingones of the plurality of second devices which most closely matchelectrical characteristics of the devices of the first network;substituting the first subset of the plurality of second devices for thefirst devices in the first network of the circuit design; assigning eachof the p-MOSFET devices in the first network to be fabricated in a firstsingle one of a plurality of tiers of a 3D IC; and assigning each of then-MOSFET devices in the first subset to be fabricated in a second singleone of the plurality of tiers different from the first single one of theplurality of tiers.

In some embodiments, a method comprises receiving a circuit designcomprising networks of first devices to be fabricated in a 3D IC havinga plurality of tiers; selecting at least a first network, a secondnetwork, and a third network within the circuit design, the secondnetwork having an equal number of p-metal oxide semiconductor fieldeffect transistors (p-MOSFET) devices and n-MOSFET devices; assigningeach device within the first network to be fabricated within a firstsingle tier of the 3D IC; assigning each of the p-MOSFET devices to befabricated in the first single tier of the 3D IC or a second single tierof the 3D IC; assigning each of the n-MOSFET devices to be fabricated ina single tier of the 3D IC different from the tier to which the p-MOSFETdevices are assigned; and assigning each respective device of the thirdnetwork to be fabricated in one or more respective tiers of the 3D ICbased on a total area of devices previously assigned to each tier beforeassigning that respective device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a stacked CMOS 3D IC.

FIGS. 2A and 2C show devices to be assigned to tiers of a 3D IC. FIGS.2B and 2D show an example of assignments for the devices of FIGS. 2A and2C, respectively.

FIG. 3 is a schematic diagram of a method for porting a circuit from afirst process technology to a second process technology, where thesecond process technology is a 3D technology.

FIG. 4 is a flow chart of a method for porting a circuit to a 3D ICtechnology.

FIG. 5 is a schematic diagram of a plurality of circuits to be ported toa 3D IC technology.

FIG. 6 is a flow chart of the group partitioning of FIG. 4.

FIG. 7 is a flow chart of the geometry matching recognition andassignment of FIG. 4.

FIG. 8 is a flow chart of the tier balanced partitioning of FIG. 4.

FIG. 9 is an example of a circuit to be assigned by the tier balancedpartitioning of FIG. 8.

FIG. 10 is a block diagram of a system according to some embodiments.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. In the description, relativeterms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,”“below,” “up,” “down,” “top” and “bottom” as well as derivative thereof(e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should beconstrued to refer to the orientation as then described or as shown inthe drawing under discussion. These relative terms are for convenienceof description and do not require that the apparatus be constructed oroperated in a particular orientation. Terms concerning attachments,coupling and the like, such as “connected” and “interconnected,” referto a relationship wherein structures are secured or attached to oneanother either directly or indirectly through intervening structures, aswell as both movable or rigid attachments or relationships, unlessexpressly described otherwise.

FIG. 1 is a cross sectional diagram of a 3D IC 100 of a type havingplural tiers 181, 182, each tier having a respective active device layer102, 152. The 3D IC can be a stacked CMOS 3D IC, a single-substrate 3DIC, or a stacked-die 3D IC, for example.

The semiconductor substrate 102 comprises silicon, a III-Vsemiconductor, an SOI substrate or the like. In some embodiments, thesemiconductor substrate 102 includes an epitaxial layer (not shown). Inother embodiments, the substrate 102 includes stressor material regions(not shown) for performance enhancement. For example, the epitaxiallayer can include semiconductor materials having a lattice structuredifferent from those of the bulk semiconductor such as a layer ofsilicon germanium overlying a bulk silicon, or a layer of siliconoverlying a bulk silicon germanium formed by a process includingselective epitaxial growth (SEG). Further, the substrate 102 can includea semiconductor-on-insulator (SOI) structure.

The substrate 102 has a plurality of active and/or passive devices 101,such as transistors, diodes, capacitors and varactors. FIG. 1 shows anexample of a single transistor 101 for ease of illustration, but an ICcan include millions or billions of such devices. The transistor 101 hasa source 104 and a drain 106 in the surface of the substrate 102, and agate insulating layer 108 and gate electrode 110 above the surface. Oneor more passivation layer and/or dielectric layer 112 are provided overthe active devices 101. The substrate 102 has an interconnect structure185 between the substrate 102 and the upper tier semiconductor layer152. The interconnect structure 185 includes contacts 114 and one ormore inter-metal dielectric (IMD) layers 112 containing conductive vias118 and/or conductive lines 116. In the example of FIG. 1, a singleconductive line layer 116 is shown. In other embodiments (not shown),additional conductive via layers and/or conductive line layers areincluded below the upper tier semiconductor layer 152. For example, thebottom tier 181 can have 8 to 14 IMD layers, each including respectiveconductive lines 116 and conductive vias 118. The IMD layers compriseSiO₂, SiON, SiN, low-k dielectric or the like.

In some embodiments, the upper tier 182 has a semiconductor layer 152,such as silicon, a III-V semiconductor or the like, for forming a secondtier of active devices 151 therein. The devices 151 include source 154,drain 156, gate insulation layer 158 and gate electrode layer 160. Insome embodiments, the upper tier semiconductor layer 152 is a thinsubstrate or wafer (e.g., from 1 micron to 10 microns in thickness)joined to the top surface of the interconnect structure 185 of the lowertier 181. Such a configuration is referred to as a stacked CMOSconfiguration. In other embodiments, the semiconductor layer 152 isdeposited over the interconnect structure 185.

The upper tier 182 has an interconnect structure 186 above the uppertier semiconductor layer 152. The interconnect structure 186 of theupper tier 182 includes dielectric layer 162 having contacts 164, atleast one conductive line layer 166 and at least one conductive vialayer 168. In some embodiments, the interconnect structure 186 has 8 to14 IMD layers. Connections between the lower tier 181 and the upper tier182 include inter-tier vias 170 which extend from a top surface of thesemiconductor layer 152 to a bottom surface of the semiconductor layer102.

In porting a circuit design from a first process to a 3D technology(second process) having N tiers, the IC area can ideally be reduced by afactor of M/N, where M is the number of dies or tiers in the firstprocess, and N is the number of tiers in the second process. Efficientpartitioning and placement of circuits in each tier determines howclosely the design approaches the ideal shrinkage.

In some embodiments predominated by differential pair circuits, thedifferential pair circuits are divided between two tiers 181, 182 of a3D IC. All of the p-MOSFETs are assigned to one single tier of the 3DIC, and all of the n-MOSFETs are assigned to a different single tier ofthe 3D IC.

FIG. 2A shows a simple circuit having one p-metal oxide semiconductorfield effect transistor (p-MOSFET) and one n-MOSFET. An inverter is anexample of a device having one p-MOSFET and one n-MOSFET. FIG. 2B showsa method of partitioning by assigning the p-MOSFET to the top tier 182and the n-MOSFET to the bottom tier 181.

FIG. 2C is a schematic diagraph of another circuit having two p-MOSFETsand 2 n-MOSFETs. FIG. 2D shows a method of partitioning by assigningboth the p-MOSFETs to the top tier 182 and both the n-MOSFET to thebottom tier 181. A NAND gate is an example of a device having twop-MOSFETs and two n-MOSFETs.

The porting procedure of FIGS. 2A-2D provides efficient usage of spacein the IC, for a design having a high degree of symmetry betweenp-MOSFETs and n-MOSFETs, and without constraints on assignment ofdevices to respective tiers.

FIG. 3 shows a more generalized approach for porting a design from afirst process (which can be either a 2D single chip technology or a 3DIC technology) to a second process different from the first process.

FIG. 3 shows a device or circuit fabricated using the first process,process A. Each device to be fabricated using the first process ischaracterized by a plurality of parameters, referred to herein asprocess electrical characteristics (PEC), such as drain current Id,threshold voltage Vt, drain-source transconductance Gds, drain sourceresistance Rds, gate current Ig, gate capacitance Cg, and off currentIoff. These PEC values can be derived from actual electronic test dataand/or SPICE level simulation. During development of the cell librariesfor a new technology node, PEC for the same parameters are determined bySPICE level simulation. Table 1 shows an example of a PEC table for afirst process to be stored in a non-transitory, machine readable storagemedium for use by a computer performing an automated process for portinga design to a new technology. Each device is characterized by physicaldesign parameters (length, width and the number of fingers), and by thecorresponding PEC.

TABLE 1 width length No. of PEC (um) (um) fingers Id Gds Gm n-MOSFET 8 11 5.70E−05 6.63E−06 5.00E−04 p-MOSFET 1 1 1 −2.70E−06   3.4E−07 1.80E−05

Table 2 shows a corresponding table for a new (second) processtechnology, to which a design will be ported.

TABLE 2 width length No. of PEC (um) (um) fingers Id Gds Gm n-MOSFET5.8  0.91 1 5.71E−05 6.62E−06 5.01E−04 1 n-MOSFET 0.74 1.24 2 5.77E−056.88E−06 5.68E−04 2 p-MOSFET 0.5  0.58 1 −2.69E−06  3.41E−07 1.81E−05 1p-MOSFET 1.04 1.84 2 −7.30E−06  3.56E−07 5.69E−05 2

Table 2 includes a plurality of n-MOSFET designs and a plurality ofp-MOSFET designs. Thus, the electrical porting block 302 of FIG. 3 takesinto account the PEC database 301, including the PEC of the firsttechnology (Table 1) and the PEC of the second technology devices inTable 2. The resulting design uses the devices of the second processtechnology to provide the same function and meet the same performancerequirements as the design when fabricated using the first technology.In addition to the electrical characteristics, the database 301 includesthe width, length, and number of fingers of each device, which can beused to compute the area of each device type. In some embodiments, thesedimensions are used to maximize area shrinkage when porting the designto the second process technology.

In some embodiments, if there is no second device having the same PEC asthe corresponding first device in the circuit design, the systemprovides the user the option to update the geometry of the closestdevice (e.g., change the gate length, gate width or number of fingersand check the PEC impact of the second process, then select thepreferred device). Should the designer choose to modify the seconddevice parameters, the processor performs a simulation (using, forexample, HSPICE, SPECTRE, ELDO, Berkely Design Automation. (EDA tools)to confirm that the modification produces PEC closer to that of theoriginal first device. Then the designer can update the dimensions(length, width, finger) in the PEC database 301.

In some embodiments, each second device design is assumed to have asingle respective set of dimensions and PEC regardless of which tierthat device is fabricated on. In other embodiments, the database 301provides greater precision by providing separate PEC and area data foreach device design, for each tier. Thus, in some embodiments, ann-MOSFET having a given set of dimensions has different PEC whenfabricated in the second tier than when the device having the samedimensions is fabricated in the first tier, and the PEC database 301includes a first set of PEC for that n-MOSFET for use when it isassigned to the first tier and a second set of PEC for that n-MOSFET foruse when it is assigned to the second tier.

FIG. 4 is a flow chart of the porting process.

At step 402, the PEC database 301 is populated with the characteristicsof the devices fabricated by the first technology and the devicesfabricated by the second technology. The PEC database includes datacorresponding a plurality of first devices fabricated by the first(older) process technology and a plurality of second devices to befabricated by the second (newer) process technology. The PEC table 301is stored in a non-transitory, machine readable storage medium.

At step 404, the programmed processor receives a circuit designcomprising a plurality of first devices fabricated by a firstfabrication process.

At step 406, the electrical matching migration is performed. Theprocessor retrieves the electrical characteristics for the plurality ofsecond devices from the table stored in a non-transitory, machinereadable storage medium. The programmed processor selects a first subsetof a plurality of second devices to be fabricated by a second process.For example, the circuit design has two transistors, one n-MOSFET andone p-MOSFET with dimensions and PEC described with reference toTable 1. The programmed processor searches to find the matching PECdevices in the second process.

Thus, a threshold decision made by the processor includes selecting thefirst subset of the second devices to include ones of the plurality ofsecond devices which most closely match the process electricalcharacteristics of the corresponding first devices. In this example, theprocessor selects the n-MOSFET1 and one of the p-MOSFET2 having matchingPEC performance.

For example, in Table 1, the n-MOSFET has a drain current of 5.70E-05and the p-MOSFET has a drain current of −2.70 E-06. Of the availabledevices in Table 2, the most closely matching n-MOSFET is n-MOSFET 1,which has a drain current of 5.71E-05; and the most closely matchingp-MOSFET is p-MOSFET 1, which has a drain current of −2.69 E-06. Thus,n-MOSFET 1 and p-MOSFET 1 are selected as the first subset of theplurality of second devices (in Table 2) to be used for fabricating thecircuit design using the second technology. The selected first subset ofthe plurality of second devices can provide performance equivalent tothat achieved using the first process technology.

At step 408, circuits and blocks of circuits are grouped according toelectrical constraints. These electrical constraints can include, forexample, matching constraints. If a network or circuit block that hasbeen fabricated and qualified using the first process technology issensitive to impedance matching, the designer can decide that suchnetwork or circuit block shall be ported together within a single tierof the 3D IC. For example, in some embodiments, the designer can chooseto group all of the active devices of an analog circuit together in thesame tier (which can be either the bottom tier or the upper tier). Thedesigner can group the devices of the analog circuit together, so thatregardless of what partitioning algorithm is applied to divide theremaining devices among the plurality of tiers, the devices of thegrouped circuit all are assigned to the same tier.

Similarly, in some embodiments, the designer can choose to group all ofthe active devices of a custom logic circuit (also referred to as thedesigner's IP) together in the same tier (either the bottom tier or theupper tier). Further, in some embodiments, the designer can choose togroup all of the active devices of a memory circuit together in the sametier (either the bottom tier or the upper tier). These are onlyexamples, and the designer can select any circuit or network, withinwhich all of the active devices are to be grouped in the same tier aseach other.

At step 410, the computer partitions the groups into tiers. The groupsare partitioned to minimize the variance of the total area of thegrouped circuits assigned to each tier. That is, the groups arepartitioned to minimize the between-partition differences between therespective sums of the areas of all grouped circuits in each partition.The partitioning of the grouped circuits into tiers is described belowwith reference to FIGS. 5 and 6.

At step 412, geometry matching recognition and assignment is performedfor the circuits and devices which are not included in any of the groupsin step 408. This step targets circuits (or networks) having equalnumbers of n-MOSFETs and p-MOSFETs. In some embodiments, the matchingrecognition is performed on the layout by comparison of polygons in theN-well and P-well respectively. In other embodiments, the matchingrecognition is performed on the netlist.

In some embodiments, this step searches for a node (e.g., node 191 inFIG. 2A or node 192 in FIG. 2C) between an n-MOSFET and an adjacentp-MOSFET within a circuit or network. Once this node 192 is found, thedesign is searched for an adjacent n-MOSFET on one side of the foundnode, and for an adjacent p-MOSFET on the other side of the found node.This search is repeated as long as equal numbers of adjacent n-MOSFETsand adjacent p-MOSFETs are found on each side of the found node. Whenthere are no more devices within the circuit or network on either sideof the found node 191, 192, the adjacent n-MOSFET's on one side of thefound node 191, 192 are assigned to a single tier of the 3D IC, and theadjacent p-MOSFET's on the other side of the found node are assigned toa different single tier of the 3D IC. For example, as shown in FIGS. 2Band 2D, all the n-MOSFET's are assigned to the lower tier 181, and allthe p-MOSFET's are assigned to the upper tier 182. In other embodiments,(not shown) all the p-MOSFET's are assigned to the lower tier 181, andall the n-MOSFET's are assigned to the upper tier 182. Further, in 3DICs having three or more tiers, the n-MOSFETs found in step 412 can allbe assigned to any of the three or more tiers, and the p-MOSFETs can allbe assigned to any other one of the three or more tiers, different thanthe tier in which the n-MOSFETs are assigned.

Further, in some embodiments having four tiers, the n-MOSFETs can beevenly divided among a first tier and a second tier, while the p-MOSFETsare evenly divided among a third tier and a fourth tier, where thefirst, second, third and fourth tiers can be stacked in any sequencewith respect to each other. In some embodiments, the processor assignseach second device in the circuit or network to the one of the pluralityof tiers for which a total area of devices previously assigned to thattier is smallest, the assigning performed sequentially according to asorting by device area.

Referring again to FIG. 4, at step 414, the processor performstier-balanced partitioning of the remaining networks and devices. Thedevices (nodes) within each circuit (network) are assigned to equalizethe total area of devices assigned to each tier.

The sequence of FIG. 4 implicitly prioritizes three partitioningmethods. First, designer-selected groups are assigned to respectivesingle tiers. Second, geometry matching recognition divides networkshaving equal numbers of p-MOSFETs and n-MOSFETs between two tiers (allp-MOSFETs assigned to one tier; all n-MOSFETs assigned to a differenttier). Third, the remaining networks are sequentially assigned, fromlargest to smallest, to approach equal area loading among tiers witheach assignment.

FIG. 5 shows an example of a set of four groups to be partitioned,corresponding to four different custom designed logic circuits (IPblocks) 501-504. Table 3 lists exemplary total areas for the four IPblocks 501-504 shown in FIG. 5.

TABLE 3 Area (μm²) IP 1 (501) 100 IP 2 (502) 50 IP 3 (503) 70 IP 4 (504)80

FIG. 6 is a flow chart of a method of grouping and partitioning circuitsand circuit blocks as briefly discussed above with reference to steps408 and 410 of FIG. 4. For example, the method of FIG. 6 can be used topartition the groups 501-504 of circuits of FIG. 5.

Note that in steps 602-608, described below, all of the devices assignedto a given group are to be fabricated in the same tier as each other. Insome embodiments, two or more of the circuits can be assigned to thesame group. In some embodiments, the number of groups is greater than orequal to the number of tiers, and less than or equal to the number ofgrouped circuits. In some embodiments, two or more groups are assignedto one or more of the tiers.

At step 602, in some embodiments, each analog circuit is assigned to arespective group.

At step 604, in some embodiments, each circuit that is sensitive toimpedance matching is assigned to a respective group.

At step 606, in some embodiments, each of the designer's custom logiccircuits is assigned to a respective group.

At step 608, in some embodiments, each memory circuit is assigned to arespective group.

At step 610, a respective total area is determined or computed for eachrespective group. In some embodiments, the area of each circuit block isdetermined by the place and route tool, and this area can be used. Insome embodiments, for each type of device in a group, the number ofdevices of that type is multiplied by the length times the width forthat device type (as stored in the PEC database 301, FIG. 3). In theexample of FIG. 5, the areas are given in Table 3, above.

At step 612, the processor sorts the groups of circuits/circuit blocksby total area. Referring to the example of FIG. 5 and Table 3, the IPblocks 501-504 are sorted into the sequence 501, 504, 503, 502.

At step 614, step 616 is repeated for each group (circuit block), fromthe largest area group to the smallest area group.

At step 616, each group is assigned to the tier with the smallest totalof previously assigned group areas. Thus, the plurality of firstcircuits are divided among the tiers of the 3D IC, so as to balance arespective sum of the total areas of the first circuits assigned to eachrespective tier of the 3D IC.

Applying steps 614 and 616 to the example of FIG. 5, IP block 1 (501) isassigned first. Assuming that no other groups have been previouslyassigned, IP block 501 is assigned to tier 1. The next largest group, IPblock 504 is assigned to the tier having the smallest total area ofpreviously assigned groups, which is now tier 2. Thus, at this stage,tier 1 has been assigned a total area of 100 μm² and tier 2 has beenassigned a total area of 80 μm². The group having the next largest areais IP block 503 (area=70 μm²). IP block 503 is assigned to tier 2, whichhas the smallest total of previously assigned areas (80 μm²). Now, thetotal area assigned to tier 2 is 150 μm², and tier 1 has the smallesttotal area of previously assigned groups (100 μm²). The last group to beassigned is IP block 502, which has an area of 50 μm², and is assignedto tier 1. Thus, the total areas of circuit blocks assigned to tier 1and tier 2 are 150 μm² each.

Although the example of FIG. 5 and Table 3 provides an exact equality ofareas assigned to each tier, in other examples and embodiments, thetotal areas of the grouped circuits assigned to each tier differ fromeach other. Nevertheless, the method of sorting the groups by totalgroup area, from largest to smallest, and assigning each groupsequentially to the tier having the smallest total area of previouslyassigned groups minimizes the differences between the total areas ofgroups assigned to each tier.

FIG. 7 is a detailed flow chart of the geometry matching recognitionstep 412 of FIG. 4

At step 702, the processor identifies the circuits and networks withinthe design which have not been grouped by the designer in step 408.

At step 706, the processor searches within the design for symmetry incircuit patterns. For example, in some embodiments, the processorlocates a node (such as node 191 in FIG. 2A, or node 192 in FIG. 2C)between an n-MOSFET and an adjacent p-MOSFET.

At step 708, the processor identifies circuits having an equal number ofp-MOSFETs and n-MOSFETs. For example, beginning at the node found instep 706, the processor identifies each adjacent p-MOSFET on a firstside of the found node for which there is a corresponding n-MOSFET onthe opposite side of the found node. The processor continues to searchfor another adjacent p-MOSFET on the first side of the found node andanother adjacent n-MOSFET on the opposite side, until either noadditional p-MOSFET is found on the first side, or no additionaln-MOSFET is found on the opposite side.

At step 710, steps 712 and 714 are performed for each identified circuithaving matching p-MOSFETs and n-MOSFETs.

At step 712, each of the identified p-MOSFETs is assigned to a first oneof the tiers (where the first tier can be the upper tier or the lowertier).

At step 714, each of the identified n-MOSFETs is assigned to a secondone of the tiers different from the first tier (where the second tiercan be the lower tier or the upper tier).

FIG. 8 is a detailed flow chart of a method for performing thetier-balanced partitioning step 414 of FIG. 4.

At step 802, the processor analyzes the area load of each remainingnetwork (third circuit) which has not been grouped and partitioned insteps 408 and 410, and has not been assigned in the geometry matchingstep 412. For each of the remaining networks, the number of devices ofeach type in the network is determined, and the number of devices ismultiplied by the area (product of length times the width) for that typeof device.

At step 804, the processor sorts the selected subset of second devicescorresponding to the remaining networks by device area, from the largestnetwork to the smallest network.

At step 806, the loop containing steps 808, 810 and 812 is performed foreach of the networks sequentially, from the largest to the smallestnetwork.

At step 808, the processor sorts the devices within the network bydevice area.

At step 810, step 812 is performed for each of the devices in thenetwork sequentially, from the largest device to the smallest device.

At step 812, the processor sequentially assigns each respective deviceof the network to be fabricated in a respective one the tiers of the 3DIC which has a smallest total area of devices assigned to that one tierbefore assigning that respective device of the network.

FIG. 9 shows an example of an SRAM sense enable generation circuit 900within a circuit design to be assigned according to the method of FIG.8. Thus, in this example, it is assumed that the sense enable generationcircuit was not previously grouped for assignment to a single tier, andthe devices of the sense enable generation circuit were not all assignedby the group matching process. (In other examples, all of the invertersand NAND gates of this sense enable generation circuit 900 arepartitioned during the geometry matching step. However, the completecircuit 900 is partitioned by the tier-balanced method for purpose ofexample).

The sense enable generation circuit 900 includes a read tracking block920 and a write cycle delay chain 299. The circuit design includes aplurality of inverters 904-913 a plurality of NAND gates 901-903, and ann-MOSFET 914. For each of these devices, the processor determines anetwork area loading corresponding to the area of that device.

In the example, each inverter has one p-MOSFET and one n-MOSFET. EachNAND gate has two p-MOSFETs and two n-MOSFETs. The area of each inverteris determined by the sum of the area of one n-MOSFET and the area of onep-MOSFET. The area of each NAND is determined by the sum of (two timesthe area of one n-MOSFET) and (two times the area of one p-MOSFET). Therespective area loading of each network is determined from thesecomputations.

The networks are sorted from largest to smallest. In this example,networks 902, 903 and 904 have the largest, 2nd largest and thirdlargest areas. Within each network, beginning with network 902, theindividual devices are sorted from largest to smallest, and thenpartitioned in sequence from largest device to smallest device. Thus, aseach device is assigned, the balance between the total areas assigned toeach tier improves. Table 4 shows the total assigned area in each tier.When network 902 is assigned, the tier loading is equal (0.0864 μm² pertier). Then, when network 903 is assigned, the area assigned to tier 1is slightly larger. Assignment of the next network 904 assigns greaterarea to tier 2, bringing the two tiers back into balance. When network913 is assigned, the area loading of tier 1 becomes larger again (50.9%versus 49.1%). Then, when network 914 is assigned, devices occupyingmore area are assigned to tier 2 to reduce the difference betweentotals. The final area balance between tiers is 49.2% in tier 1 and50.8% in tier 2.

TABLE 4 Tiers net 902 net 903 net 904 net 912 net 913 net 914 Balancetier 1 0.0864 0.1008 0.108 0.1944 0.2088 0.2088 49.2% area (μm²) tier 20.0864 0.0936 0.108 0.1944 0.2016 0.2160 50.8% area (μm²)

The above described methods permit the user to substantially equalizethe area loading of each tier, to permit the maximum shrinkage for thetarget process technology. Depending on how close the shrinkage is tothe ideal 50% split for migrating from a single tier to two tiers, theuser can make additional adjustments to the partitioning to improve thebalance. Alternatively, the user can add dummy devices to the tierhaving a smaller total area load, to further reduce any differencebetween the total area of devices assigned to each tier.

FIG. 10 is a block diagram of a system for performing the methoddescribed herein.

FIG. 10 is a block diagram of a system 1000 for providing layouts andperforming the multi-patterning decomposition for the layer of thesubstrate, according to one embodiment. Block 1002 indicates that one ormore programmed processors may be included. In some embodiments, theprocessing load is performed by two or more application programs, eachoperating on a separate processor. In other embodiments, the processesare all performed using one processor. Similarly, two non-transitorymachine readable storage media 1006 and 1008 are shown, but the data maybe stored in any number of media. Although FIG. 10 shows an allocationof the various tasks to specific modules, this is only one example. Thevarious tasks may be assigned to different modules to improveperformance, or improve the ease of programming.

System 1000 includes an electronic design automation (“EDA”) tool suchas “IC COMPILER”™, sold by Synopsys, Inc. of Mountain View, Calif.,which may include a place and route tool 1004, such as “ZROUTE”™, alsosold by Synopsys. Other EDA tools may be used, such as the “VIRTUOSO”custom design platform or the Cadence “ENCOUNTER”® digital IC designplatform may be used, along with the “VIRTUOSO” chip assembly router1004, all sold by Cadence Design Systems, Inc. of San Jose, Calif.

The EDA tool is a special purpose computer formed by retrieving storedprogram instructions from a non-transient computer readable storagemedium 1006 and executing the instructions on a general purposeprocessor 1002. Thus, the instructions configure the logic circuits ofthe processor 1002 to function as an EDA tool. Examples of non-transientcomputer readable storage mediums 1006, 1008 include, but are notlimited to, hard disk drives (HDD), read only memories (“ROMs”), randomaccess memories (“RAMs”), flash memories, or the like. Tangible,non-transient machine readable storage mediums 1006, 1008 are configuredto store data generated by the place and route tool 1004.

The router of the place and route tool 1004 is capable of receiving anidentification of a plurality of cells to be included in an integratedcircuit (“IC”) or interposer layout, including a netlist 1020 containingpairs of cells within the plurality of cells to be connected to eachother. Router 1004 may be equipped with a set of default design rules1022 and technology file 1024. The medium 1006 also contains the PECdatabase 301, including the process electrical characteristics anddimensions (or area) of each device.

A module 1005 queries the user to input electrical constraints, such asdesigner selection of devices, circuits or networks to be groupedtogether to ensure impedance matching is maintained.

In some embodiments, a graphical interface facilitates the designprocess by displaying the design layout or portions of the layout, suchas those described above on a display 1030. The display 1030 allows thedesigner to view the main function blocks (e.g., IP blocks) and toselect any network to be included in a group of devices to be includedin a single partition (tier).

A module 1010 performs electrical migration matching. The modulereceives the circuit design, and designations of the first (old)technology and second (new) process technology. The module 1010identifies each core device (e.g., transistor, diode, capacitor,varactor or the like) in the received circuit design. The module 1010queries the PEC database 301 to find corresponding devices fabricated bythe target second process technology which have the same or similar PECas corresponding devices made by the first process. In some embodiments,if a single second device is found having the same PEC as the firstdevice, the module 1010 automatically selects that found device to besubstituted for the first device. In other embodiments, module 1010 asksthe user to confirm the selection, even if the found device is the onlyexact match. In some embodiments, if two or more second devices arefound having PEC the same as or close to the PEC of the first device,the PEC of all the found second devices are displayed, to allow the userto select one of the second devices.

A module 1012 partitions the networks and circuits previously grouped bythe designer (such as IP blocks, analog circuits, memory blocks, orother circuits sensitive to impedance matching. The module sorts thegroups by area, from largest to smallest. Then, beginning with the grouphaving the largest area, the module determines which tier has thesmallest total of previously assigned groups, and assigns the next groupis assigned to the tier having the smallest total area. For eachsuccessive group, the steps of computing the total area of each tier andassigning that group to the tier having the smallest total area arerepeated.

A geometry matching module 1014 recognizes symmetry between n-MOSFETsand p-MOSFETs within a network of the design, assigns the n-MOSFETs ofthat network to one tier and assigns the p-MOSFETs of that network toanother different tier. In some embodiments, module 1014 is configuredto search for a node that is directly connected to an adjacent n-MOSFETand an adjacent p-MOSFET. When such a node is found, the module 1014searches for additional adjacent matching n-MOSFET, p-MOSFET pairsconnected to the found n-MOSFET, p-MOSFET pair. This search is repeateduntil no more complete, connected n-MOSFET, p-MOSFET pairs are found.

A tier balance partitioning module 1016 determines the total areas ofremaining networks, sorts the remaining networks from largest total areato smallest total area, and sequentially partitions each network fromthe largest to the smallest. Within each network module 1016 sorts thedevices by device area, and sequentially assigns each device (from thelargest device to the smallest) to the tier having the smallest totalarea of previously assigned groups, networks and devices.

The pattern layout with tier assignments 1018 are then stored in anon-transitory machine-readable storage medium 1008.

In some embodiments, a method comprises: receiving a circuit designcomprising networks of first devices fabricated by a first fabricationprocess; selecting second devices to be fabricated by a second process;substituting the second devices for the first devices in the networks ofthe circuit design; sorting the second devices within a selected one ofthe networks by device area from largest device area to smallest devicearea; and assigning each second device in the selected network to befabricated in a respective one of a plurality of tiers of a 3D IC forwhich a total area of second devices previously assigned to that tier issmallest, the second devices being assigned sequentially according tothe sorting.

In some embodiments, the selecting includes selecting a first subset ofa plurality of second devices to be fabricated by a second process, thefirst subset including ones of the plurality of second devices whichmost closely match electrical characteristics of the corresponding firstdevices.

Some embodiments further comprise retrieving the electricalcharacteristics and dimension s for the plurality of second devices froma table stored in a non-transitory, machine readable storage medium,before the selecting step.

In some embodiments, each network has a plurality of second devices anda total device area, and the method further comprises sorting theplurality of networks by the total device area of each respectivenetwork, wherein for each respective network, the devices of thatrespective network are assigned sequentially according to the sorting ofthe plurality of networks by device area.

Some embodiments further comprise: assigning each second device in asecond one of the networks to a single one of the plurality of tiers.

In some embodiments, the step of assigning each of the second devices inthe second network is performed before the step of assigning each of thesecond devices in the first network.

In some embodiments, the second network comprises an analog circuit.

In some embodiments, the second network comprises a custom logiccircuit.

In some embodiments, the second network comprises a memory circuit.

Some embodiments further comprise: identifying at least one additionalcircuit included in the circuit design, wherein the additional circuitincludes an equal number of p-metal oxide semiconductor field effecttransistors (p-MOSFET) and n-MOSFET devices; assigning each of thep-MOSFET devices in the additional circuit to a first single one of theplurality of tiers; and assigning each of the n-MOSFET devices in theadditional circuit to a second single one of the plurality of tiersdifferent from the first single one of the plurality of tiers.

Some embodiments further comprise: identifying a second additionalcircuit included in the circuit design, wherein the second additionalcircuit includes an equal number of p-MOSFET and n-MOSFET devices;assigning each of the p-MOSFET devices in the second additional circuitto the first single one of the plurality of tiers; and assigning each ofthe n-MOSFET devices in the second additional circuit to the secondsingle one of the plurality of tiers.

In some embodiments, the identifying includes: finding a node adjacentto and between a first p-MOSFET device and a first n-MOSFET device,searching for an additional p-MOSFET sequentially connected on a sameside of the found node as the first p-MOSFET, and searching for acorresponding additional n-MOSFET sequentially connected on a same sideof the found node as the first n-MOSFET; and repeating the searchinguntil there is no further sequentially connected p-MOSFET on the sameside of the first p-MOSFET as the first p-MOSFET, or no correspondingsequentially connected n-MOSFET on the same side of the first n-MOSFETas the first n-MOSFET

In some embodiments, the steps of assigning each of the p-MOSFET devicesand each of the n-MOSFET devices are performed before the sorting step.

In some embodiments, the additional circuit is one of the groupconsisting of an inverter, a NAND gate, a NOR gate, and a MOSdifferential pair circuit. In other embodiments, the additional circuitis any combinational or sequential circuit, such as an inverter, atransmission gate, a NAND gate, a NOR gate, a multiplexer (e.g., amultiplexer acting as a NOT gate), a latch, a flip-flop, an exclusive-OR(XOR) gate, a current mirror circuit, or a differential pair circuit.

In some embodiments, a method comprises; receiving a circuit designcomprising networks of first devices fabricated by a first fabricationprocess; identifying a first one of the networks included in the circuitdesign, wherein the first network includes an equal number of p-metaloxide semiconductor field effect transistors (p-MOSFET) devices andn-MOSFET devices; selecting a first subset of a plurality of seconddevices to be fabricated by a second process, the first subset includingones of the plurality of second devices which most closely matchelectrical characteristics of the devices of the first network;substituting the first subset of the plurality of second devices for thefirst devices in the first network of the circuit design; assigning eachof the p-MOSFET devices in the first network to be fabricated in a firstsingle one of a plurality of tiers of a 3D IC; and assigning each of then-MOSFET devices in the first subset to be fabricated in a second singleone of the plurality of tiers different from the first single one of theplurality of tiers.

In some embodiments, the identifying includes finding a node adjacent toand between an first p-MOSFET device and a first n-MOSFET device,searching for an additional p-MOSFET sequentially connected on a sameside of the found node as the first p-MOSFET, and searching for acorresponding additional n-MOSFET sequentially connected on a same sideof the found node as the first n-MOSFET; and repeating the searchinguntil there is no further sequentially connected p-MOSFET on the sameside of the first p-MOSFET as the first p-MOSFET, or no correspondingsequentially connected n-MOSFET on the same side of the first n-MOSFETas the first n-MOSFET.

In some embodiments, a method comprises receiving a circuit designcomprising networks of first devices to be fabricated in a 3D IC havinga plurality of tiers; selecting at least a first network, a secondnetwork, and a third network within the circuit design, the secondnetwork having an equal number of p-metal oxide semiconductor fieldeffect transistors (p-MOSFET) devices and n-MOSFET devices; assigningeach device within the first network to be fabricated within a firstsingle tier of the 3D IC; assigning each of the p-MOSFET devices to befabricated in the first single tier of the 3D IC or a second single tierof the 3D IC; assigning each of the n-MOSFET devices to be fabricated ina single tier of the 3D IC different from the tier to which the p-MOSFETdevices are assigned; and assigning each respective device of the thirdnetwork to be fabricated in one or more respective tiers of the 3D ICbased on a total area of devices previously assigned to each tier beforeassigning that respective device.

In some embodiments, the circuit design includes a plurality of firstnetworks, each having a respective total area, each respective firstnetwork having a plurality of devices that are to be assigned to arespective single tier of the 3D IC, and the assigning step includesdividing the plurality of first network among the tiers of the 3D IC soas to balance a respective sum of the total areas of the first networksassigned to each respective tier of the 3D IC.

In some embodiments, the step of dividing the plurality of firstnetworks among the tiers of the 3D IC includes: sorting the firstnetworks by total area from largest to smallest; and sequentiallyassigning each respective first network to be fabricated in a respectiveone the tiers of the 3D IC which has a smallest total area of firstnetworks previously assigned to that one tier before assigning thatrespective first network.

In some embodiments, the step of assigning each respective device of thethird network includes: sorting the devices within the third network bydevice area; and sequentially assigning each respective device of thethird network to be fabricated in a respective one the tiers of the 3DIC which has a smallest total area of devices assigned to that one tierbefore assigning that respective device of the third network.

The methods and system described herein may be at least partiallyembodied in the form of computer-implemented processes and apparatus forpracticing those processes. The disclosed methods may also be at leastpartially embodied in the form of tangible, non-transitory machinereadable storage media encoded with computer program code. The media mayinclude, for example, RAMs, ROMs, CD-ROMs, DVD-ROMs, BD-ROMs, hard diskdrives, flash memories, or any other non-transitory machine-readablestorage medium, wherein, when the computer program code is loaded intoand executed by a computer, the computer becomes an apparatus forpracticing any of the methods described herein. The methods may also beat least partially embodied in the form of a computer into whichcomputer program code is loaded and/or executed, such that, the computerbecomes a special purpose computer for practicing the methods. Whenimplemented on a general-purpose processor, the computer program codesegments configure the processor to create specific logic circuits. Themethods may alternatively be at least partially embodied in a digitalsignal processor formed of application specific integrated circuits forperforming the methods.

Although the subject matter has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodiments,which may be made by those skilled in the art.

What is claimed is:
 1. A computer-implemented method comprising: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from a largest device area to a smallest device area; and assigning each second device in the selected network to be fabricated in a respective tier of a plurality of tiers of a three dimensional integrated circuit (3D IC) for which a total area of second devices previously assigned to said respective tier is the smallest among that of the tiers of the 3D IC, the second devices being assigned sequentially according to the sorting wherein a computer performs the assigning.
 2. The method of claim 1, wherein the selecting includes selecting a first subset of a plurality of second devices to be fabricated by the second process, the first subset including ones of the plurality of second devices which most closely match electrical characteristics of corresponding first devices.
 3. The method of claim 2, further comprising: retrieving the electrical characteristics and dimensions for the plurality of second devices from a table stored in a non-transitory, machine readable storage medium, before the selecting step.
 4. The method of claim 1, wherein: each network has a plurality of second devices and a total device area, and the method further comprises sorting the plurality of networks by the total device area of each respective network, wherein for each respective network, the devices of that respective network are assigned sequentially according to the sorting of the plurality of networks by device area.
 5. The method of claim 1, further comprising: assigning each of the second devices in a second one of the networks to a single network of the plurality of tiers.
 6. The method of claim 5, wherein the step of assigning each of the second devices in the second network is performed before the step of assigning each of the second devices in the selected network.
 7. The method of claim 5, wherein the second network comprises an analog circuit.
 8. The method of claim 5, wherein the second network comprises a custom logic circuit.
 9. The method of claim 5, wherein the second network comprises a memory circuit.
 10. The method of claim 1, further comprising: identifying at least one additional circuit included in the circuit design, wherein the additional circuit includes an equal number of p-metal oxide semiconductor field effect transistors (p-MOSFET) devices and n-MOSFET devices; assigning each of the p-MOSFET devices in the additional circuit to a first single one of the plurality of tiers; and assigning each of the n-MOSFET devices in the additional circuit to a second single one of the plurality of tiers different from the first single one of the plurality of tiers.
 11. The method of claim 10, further comprising: identifying a second additional circuit included in the circuit design, wherein the second additional circuit includes an equal number of p-MOSFET devices and n-MOSFET devices; assigning each of the p-MOSFET devices in the second additional circuit to the first single one of the plurality of tiers; and assigning each of the n-MOSFET devices in the second additional circuit to the second single one of the plurality of tiers.
 12. The method of claim 10, wherein the identifying includes: finding a node adjacent to and between a first p-MOSFET device and a first n-MOSFET device, searching for an additional p-MOSFET device sequentially connected on a same side of the found node as the first p-MOSFET device, and searching for a corresponding additional n-MOSFET device sequentially connected on a same side of the found node as the first n-MOSFET device; and repeating the searching until there is no further sequentially connected p-MOSFET device on the same side of the first p-MOSFET device as the first p-MOSFET device, or no corresponding sequentially connected n-MOSFET device on the same side of the first n-MOSFET device as the first n-MOSFET device.
 13. The method of claim 10, wherein the steps of assigning each of the p-MOSFET devices and each of the n-MOSFET devices are performed before the sorting step.
 14. The method of claim 10, wherein the additional circuit is a combinational or sequential circuit from a group consisting of an inverter, a transmission gate, a NAND gate, a NOR gate, a multiplexer, a latch, a flip-flop, an exclusive-OR (XOR) gate, a current mirror circuit, or a differential pair circuit.
 15. A computer-implemented method comprising: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; identifying a first network of the networks included in the circuit design, wherein the first network includes an equal number of p-metal oxide semiconductor field effect transistors (p-MOSFET) devices and n-MOSFET devices; selecting a first subset of a plurality of second devices to be fabricated by a second process, the first subset including ones of the plurality of second devices which most closely match electrical characteristics of the first devices of the first network; substituting the first subset of the plurality of second devices for the first devices in the first network of the circuit design; assigning, by a computer, each of the p-MOSFET devices in the first network to be fabricated in a first single one of a plurality of tiers of a three dimensional integrated circuit (3D IC); and assigning, by the computer, each of the n-MOSFET devices in the first subset to be fabricated in a second single one of the plurality of tiers different from the first single one of the plurality of tiers.
 16. The method of claim 15, wherein the identifying includes finding a node adjacent to and between an first p-MOSFET device and a first n-MOSFET device, searching for an additional p-MOSFET device sequentially connected on a same side of the found node as the first p-MOSFET device, and searching for a corresponding additional n-MOSFET device sequentially connected on a same side of the found node as the first n-MOSFET device; and repeating the searching until there is no further sequentially connected p-MOSFET device on the same side of the first p-MOSFET device as the first p-MOSFET device, or no corresponding sequentially connected n-MOSFET device on the same side of the first n-MOSFET device as the first n-MOSFET device.
 17. A computer-implemented method comprising: receiving a circuit design comprising networks of first devices to be fabricated in a three dimensional integrated circuit (3D IC) having a plurality of tiers; selecting at least a first network, a second network, and a third network within the circuit design, the second network having an equal number of p-metal oxide semiconductor field effect transistors (p-MOSFET) devices and n-MOSFET devices; assigning each device within the first network to be fabricated within a first single tier of the 3D IC; assigning, by a computer, each of the p-MOSFET devices to be fabricated in the first single tier of the 3D IC or a second single tier of the 3D IC; assigning, by the computer, each of the n-MOSFET devices to be fabricated in a single tier of the 3D IC different from the tier to which the p-MOSFET devices are assigned; and assigning, by the computer, each respective device of the third network to be fabricated in one or more respective tiers of the 3D IC based on a total area of devices previously assigned to each tier before assigning that respective device.
 18. The method of claim 17, wherein the circuit design includes a plurality of first networks, each having a respective total area, each respective first network having a plurality of devices that are to be assigned to a respective single tier of the 3D IC, and the assigning each device within the first network step includes dividing the plurality of first network among the tiers of the 3D IC so as to balance a respective sum of the total areas of the first networks assigned to each respective tier of the 3D IC.
 19. The method of claim 18, wherein the step of dividing the plurality of first networks among the tiers of the 3D IC includes: sorting the first networks by total area from a largest total area to a smallest total area; and sequentially assigning each respective first network to be fabricated in a respective one the tiers of the 3D IC which has a smallest total area of first networks previously assigned to that one tier before assigning that respective first network.
 20. The method of claim 18, wherein the step of assigning each respective device of the third network includes: sorting the devices within the third network by device area; and sequentially assigning each respective device of the third network to be fabricated in a respective one the tiers of the 3D IC which has a smallest total area of devices assigned to that one tier before assigning that respective device of the third network. 